Now, electrical engineers at UCLA have designed a new type of computer chip that takes advantage of increasingly underutilized processing areas.
The problem of inefficiency in dark silicon areas has arisen over the past decade. As transistors have continued to get smaller, the chip’s power consumption has remained the same, leading to power outages if all transistors are used simultaneously. To stay within the power limit, only transistors in certain areas are “on” at a time. However, the usage areas are usually occupied by power-efficient but inflexible hardware accelerator blocks designed to perform an increasing number of hard-coded functions.
Led by Dejan Markovic, professor of electrical and computer engineering at the UCLA Samueli School of Engineering, the team introduced a new power-efficient chip design that maximizes areas reserved for intensive data processing while minimizing areas of black silicon. . Earlier this year, the UCLA researchers presented their study to the International Semiconductor Circuit Conference 2022. This was the only paper written by a group of academic researchers, with industry representatives making the rest of the presentations.
“Key to our chip design is its network of multiple connection layers on the core processing elements. This minimizes delays and maximizes the total area used,” said Dejan Markovic.
“Key to our chip design is its network of multiple connection layers on the core processing elements. This minimizes delays and maximizes the total area used,” Markovic said. “Like a network of synchronized traffic lights , the smart grid efficiently moves and manages data processing and computing applications across the network of billions of transistors.”
According to the researchers, the operation of their network is driven by real-time usage statistics as well as a switch box that controls which parts of the processing elements are used, thereby maximizing energy efficiency. The design is also reconfigurable, so it can be tailored to specific applications.
Entitled “A 785GMACs/J 784-Core 16 nm digital signal processor die with a multi-layer switch box interconnect, assembled as a 2×2 Dielet with 10 μm pitch inter-Dielet I/O for multi-layer reconfiguration Runtime programs», the document is available at the IEEE Xplore library.
The other authors are UCLA graduate students Uneeb Rathore and Sumeet Singh Nagi, and Subramanian Iyer, Distinguished Professor of Electrical and Computer Engineering at UCLA Samueli and Charles P. Reames Chair of Electrical Engineering.